Multicore SoC architecture from TI for communications infrastructure equipment apps

Texas Instruments has boosted the performance of its SoC class DSP integrated chips by unveiling a new System-on-a-Chip (SoC) architecture that integrates fixed and floating-point capabilities for high performing CPU. Clocking up to 1.2GHz with processor performance of 256 GMACS and 128 GFLOPS, TI's multicore SoCs are made to meet the processing demand of high bandwidth communication and wireless base stations, media gateways and video infrastructure equipment. By unveiling this new family, TI joins Freescale Semiconductor, who has also announced high performance DSP integrated multi core processors for telecom and wireless applications. The performance of the new DSP chips from TI and Freescale Semiconductor will attract the attention of telecom designers to design their products without the complexity of FPGA and the associated higher cost.

The Key features of the TI's multicore SoCs are,
Suite of tools, application-specific software libraries and platform software for fast development and debugging
TI claims, five times the DMA capability and twice the memory per core of other SoCs ensuring robust application performance.
Direct communication between cores and memory access with TI's Multicore Navigator freeing peripheral access and unleashing multicore performance
A 2 terabit per second on-chip switch fabric, TeraNet 2, providing high bandwidth and low latency interconnection of all of the SoC elements
A Multicore Shared Memory Controller allowing fast on-chip and external memory access
High-performance layer 1, layer 2 and network co-processors

"If TI delivers on its performance projections, it will clearly be raising the bar on performance for mainstream DSPs," said the respected technology analysis firm BDTI in its InsideDSP newsletter. "TI's decision to focus more on providing a multicore programming development methodology and environment could give TI an ease-of-use edge over other DSP processor vendors."
"Manufacturers of communications infrastructure equipment have very specific requirements for differentiating their products and innovating beyond a single portfolio. It was clear to us that TI had the opportunity to introduce a new platform to customers with a 'smart design' approach that meets their needs for years to come," said Brian Glinsman, general manager of TI's communications infrastructure business. "With this new multicore architecture, we challenged ourselves to exceed Moore's Law by bucking the trend of simply linearly increasing the amount of cores on each platform; instead, we increased overall performance with significant enhancements to the DSP, a new breed of coprocessors, and reduced power consumption."

For more details visit www.ti.com

To know about Freescale's similar announcement read another article
New six-core processor from Freescale Semiconductor eliminates use of FPGA in telecom