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Date: 03-01-17

Happy verification using SystemVerilog

Verilog programmers who are not familiar with System Verilog wonder what's great about System Verilog! System Verilog is a superset of verilog. It embodies OOPS concepts such as polymorphism, encapsulation, arrays (packed and unpacked arrays), and classes. These and other features of System Verilog ensure that your verification cycle time is reduced by 40%. This language is not only ensures reduced time taken for verification, but also gives that extra edge of testing with more complex tests of your Design Under Test which otherwise wouldn't have been possible using legacy HDL's verification methodologies (verilog and vhdl).

Its not that only SystemVerilog is the de-facto HVL to be used for verification purpose, but there are other HDLs such as Specman e, system c, which do offer wide variety of features for testability purposes. The advantages of SystemVerilog over Specman e, and SystemVerilog is not coupled to one particular one Vendor. It also addresses issues related to synthesis. Some constructs of SystemVerilog can be synthesized and hence ensures optimal code. SystemVerilog Assertions can be placed between RTL code and this ensures some verification load is given to designers.

If we look at the features, which SystemVerilog promises us to use, and ensures verification time cycle reduction and smooth testing; arrays is a major feature in SystemVerilog. Arrays enable the user in collecting similar data items that can be selected by indices computed at run-time. A lot can be done using arrays.

Concepts such as objects, constructs, polymorphism, inheritance and subclasses, data hiding, encapsulation, accessing class members and scope resolution are used effectively for creating a reusable and robust verification environment. The most used feature is assertions. Assertions validate assumptions, checks conditions and indicate that the system should behave in a particular manner. Lot of current EDA tools support most of the assertion types.

Other notable features of SystemVerilog include creating interfaces, providing high level of reusability, clocking blocks, packages, program blocks, processes, randomization, loops and literals. Some features are even synthesized. In future we will be seeing most of the SystemVerilog constructs being synthesized.

So! Happy verification using SystemVerilog.


To learn more on system verification, read this language reference manual at www.vhdl.org/sv/*SystemVerilog*_3.1a.pdf

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