MODULE -14
Flash memory
basics and its interface to a processor:
Introduction:
Flash memory or a flash RAM is a type of nonvolatile semiconductor
memory device where stored data exists even when memory
device is not electrically powered. It's an improved version
of electrically erasable programmable read-only memory (EEPROM).
The difference between Flash Memory and EEPROM are, EEPROM
erases and rewrite its content one byte at a time or in
other words, at byte level. Where as Flash memory erases
or writes its data in entire blocks, which makes it a very
fast memory compared to EEPROM. Flash memory can't replace
DRAM and SRAM because the speed at which the DRAM/SRAM can
access data and also their ability to address at byte level
can't be matched by Flash.
The flash memory is also termed as Solid-state Storage
Device (SSD) due to the absence of moving parts in comparison
to traditional computer hard disk drive.
Flash memory types:
The two main types of flash memory are the NOR Flash &
NAND Flash. Intel is the first company to introduce commercial
(NOR type) flash chip in 1988 and Toshiba released world's
first NAND-flash in 1989.
NOR-flash is slower in erase-operation and write-operation
compared to NAND-flash. That means the NAND-flash has faster
erase and write times. More over NAND has smaller erase
units. So fewer erases are needed. NOR-flash can read data
slightly faster than NAND.
NOR offers complete address and data buses to randomly
access any of its memory location (addressable to every
byte). This makes it a suitable replacement for older ROM
BIOS/firmware chips, which rarely needs to be updated. Its
endurance is 10,000 to 1,000,000 erase cycles. NOR is highly
suitable for storing code in embedded systems. Most of the
today's microcontrollers comes with built in flash memory.
NAND-flash occupies smaller chip area per cell.
This maker NAND available in greater storage densities and
at lower costs per bit than NOR-flash. It also has up to
ten times the endurance of NOR-flash. NAND is more fit as
storage media for large files including video and audio.
The USB thumb drives, SD cards and MMC cards are of NAND
type.
NAND-flash does not provide a random-access external address
bus so the data must be read on a block-wise basis (also
known as page access), where each block holds hundreds to
thousands of bits, resembling to a kind of sequential data
access. This is one of the main reasons why the NAND-flash
is unsuitable to replace the ROM, because most of the microprocessors
and microcontrollers require byte-level random access.
A write operation in any type of flash device can only
be performed on an empty or erased unit. So in most cases
write operation must be preceded by an erase operation.
The erase operation is fairly straightforward in the case
of NAND-flash devices. But for a NOR-flash, it is mandatory
that all bytes in the target block should be written with
zeros before they can be erased.
The size of an erase-block in NOR-flash ranges from 64
to 128 Kbytes. Here a write/erase operation can take up
to 5 s. But the NAND-flash has erase blocks 8 to 32 Kbytes
in size. So it is obvious that the NAND performs the identical
operation in a lesser time duration.
INOR-flash interface resembles closely to a SRAM memory
interface, which has enough address pins to map its entire
media, allowing for easy access to every byte contained
in it, where as the NAND-flash go for serially accessed
complicated I/O mapped interface. Here the same pins are
used for control, address & data.
In traditional single-level cell flash devices, each cell
stores only one bit of information. Later, many developers
have developed a new form of flash memory known as multi-level
cell flash that can store/hold more than one bits rather
than a single bit in each memory cell, thus doubling the
capacity of memory.
Flash memory cell structure:
Flash memory stores data in an array of memory cells. The
memory cells are made from floating-gate MOSFETS (known
as FGMOS). These FG MOSFETs (or FGMOS in short) have the
ability to store an electrical charge for extended periods
of time (2 to 10 years) even without a connecting to a power
supply.
The FGMOS is actually fabricated by electrically isolating
the gate of a standard MOS transistor, so that there are
no resistive connections to this gate (floating gate) (see
Fig 1). A secondary gate (more than one in the case of multiple
gate transistor) known as control gate is then deposited
above this floating gate and is electrically isolated from
it using an insulator like Si02. There will be only capacitive
connection between the new inputs (control gates) and the
floating gate, because the floating gate is completely surrounded
by highly resistive material (SiO2). So, in terms of its
DC operating point, the FG is a floating node.
The names, NOR-flash & NAND-flash came from the structure
used for the interconnections between memory cells (see
fig 3).
Cells in NOR-flash are connected in parallel to the bit
lines so that each cell can be read/write/erase individually.
This parallel connection of cells closely resembles to the
parallel connection of transistors in a CMOS NOR gate, that's
how it derives the name as NOR flash. In NAND-flash, cells
are connected in series resembling a NAND gate, and so the
name. The series connection prevents the cells from being
programmed individually. These cells must be read in series.
Fig 3
A typical flash-array has a grid of columns and rows of
FGMOS-transistor cells as shown in the Fig 4. The word line
WL is the horizontal line and bit line BL is the vertical
line (shown in Fig 4). The Control gates of the FGMOS cells
are connected to the word-line WL. The decoded address is
actually applied to this word-line. The bit line BL connects
drains of the FGMOS cells together and represent data bus.
The Source-line SL connects sources of the FGMOS to common
ground. The voltage combinations applied to WL and BL define
an operation, whether it is read, erase or program.
Fig 4
Working principle:
Flash stores the data by removing or putting electrons
on its floating gate (see fig 5). Charge on floating gate
affects the threshold of the memory element. When electrons
are present on the floating gate, no current flows through
the transistor, indicating a logic-0. When electrons are
removed from the floating gate, the transistor starts conducting,
indicating a logic-1. This is achieved by applying voltages
between the control gate and source or drain.
Fig 5
Fowler-Nordheim (F-N) Tunneling and hot-electron injection
are some of the process by which these operations are carried
out in the flash cell.
Tunneling is a process where electrons are transported
through a barrier. Here the barrier is considered as the
thickness of the Si02 insulator layer surrounding the floating
gate. The tunneling process in oxide was first reported
by Fowler and Nordheim, so the name.
Let us now try to know how a NOR-flash cell operates. In
NOR-flash program (or the memory write) is carried out via
"hot electron injection" and erase via quantum
tunneling.
1. Erase operation:
The raw state of flash memory cells (A single-level NOR
flash cell) will be bit 1's, (at default state) because
floating gates carry no negative charges. Erasing a flash-memory
cell (resetting to a logical 1) is achieved by applying
a voltage across the source and control gate (word line).
The voltage can be in the range of -9V to -12V. And also
apply around 6V to the source. The electrons in the floating
gate are pulled off and transferred to the source by quantum
tunneling (a tunnel current). In other words, electrons
tunnel from the floating gate to the source and substrate.
2. Write (program) operation:
A NOR flash cell can be programmed, or set to a binary
"0" value, by the following procedure.
While writing a high voltage of around 12V is applied to
the control gate (word line). If high voltage around 7V
is applied to Bit Line (Drain terminal), bit 0 is stored
in the cell. The channel is now turned on, so electrons
can flow from the source to the drain. Through the thin
oxide layer electrons move to the floating gate. The source-drain
current is sufficiently high to cause some high-energy electrons
to jump through the insulating layer onto the floating gate,
via a process called hot-electron injection.
Due to applied voltage at floating-gate the excited electrons
are forced through and trapped on other side of the thin
oxide layer, giving it a negative charge on the floating
gate. These negatively charged electrons act as a barrier
between the control gate and the floating gate.
If low voltage is applied to the drain via the bit line,
the amount of electrons on the floating gate remains the
same, and logic state doesn't change, storing the bit 1.
Since floating gate is insulated by oxide, the charge accumulated
on the floating gate will not leak out, even if the power
is turned off.
A device called a cell sensor watches the level of the charge
passing through the floating gate. If the flow through the
gate crosses 50 percent threshold, it has a value of 1.
When the charge passing through decline to below 50-percent
threshold, than the value changes to 0.
Because of the very good insulation properties of SiO2,
the charge on the floating gate leaks away very slowly.
3. Read operation:
Apply a voltage around 5V to the control gate and around
1V to the drain. The state of the memory cell is distinguished
by the current flowing between the drain and the source.
To read the data, a voltage is applied to the control gate,
and the MOSFET channel will be either conducting or remain
insulating, based on the threshold voltage of the cell,
which is in turn controlled by charge on the floating gate.
The current flow through the MOSFET channel is sensed and
forms a binary code, reproducing the stored data.
Flash Memory Interfacing:
Flash memory interface is same as SRAM interface, except
that the flash memory requires a 12V/5V programming voltage
to erase and write new data.
Fig 6
The above figure is the schematic circuit diagram of a
NOR flash IC 28F400 from Intel interfaced to a 16-bit (data)
processor or a microcontroller. The 28F400 can be configured
as 512K x 8 memory device or as a 256K x 16 memory device.
Here in the above case its 512K x 8 configuration. The control
connections pins CE, OE & WE are similar to SRAM interface.
The A0 - A17 are address pins and DQ0 to DQ15 are data
pins.
The function of each control pins are,
OE (OUTPUT ENABLE): Enables the device's outputs
through the data buffers during a read cycle. OE is active
low.
WE (WRITE ENABLE): Controls writes to the command
register and array blocks. WE is active low. Addresses and
data are latched on the rising edge of the WE pulse.
CE (CHIP ENABLE): Activates the device's control
logic, input buffers, decoders and sense amplifiers. CE
is active low. CE high de-selects the memory device and
reduces power consumption to standby levels. If CE and RP
are high, but not at a CMOS high level, the standby current
will increase due to current flow through the CE and RP
input stages.
BYTE: Configures whether the device operates in byte-wide
mode (x8) or word-wide mode (x16). This pin must be set
at power-up or return from deep power-down and not changed
during device operation. BYTE pin must be controlled at
CMOS levels to meet the CMOS current specification in standby
mode.
When BYTE is at logic low, the byte-wide mode is enabled,
where data is read and programmed on DQ0-DQ7 and DQ15/A-1
becomes the lowest order address that decodes between the
upper and lower byte. DQ8-DQ14 are tri-stated during the
byte-wide mode.
When BYTE is at logic high, the word-wide mode is enabled,
where data is read and programmed on DQ0-DQ15.
Vpp (PROGRAM/ERASE POWER SUPPLY): For erasing memory
array blocks or programming data in each block, a voltage
either of 5 V ± 10% or 12 V ± 5% must be applied
to this pin. When VPP < VPPLK all blocks are locked and
protected against Program and Erase commands.
RP/PWD (RESET/DEEP POWER-DOWN): Uses three voltage
levels (VIL, VIH, and VHH) to control two different functions:
reset/deep power-down mode and boot block unlocking. It
is backward compatible with the BX/BL/BV products. When
RP is at logic low, the device is in reset/deep power-down
mode, which puts the outputs at High-Z, resets the Write
State Machine, and draws minimum current.
When RP is at logic high, the device is in standard operation.
When RP transitions from logic-low to logic-high, the device
defaults to the read array mode.
When RP is at VHH, the boot block is unlocked and can be
programmed or erased. This overrides any control from the
WP input.
The decoder IC 74LS139 is employed in the above circuit
for selecting the flash memory through A19 and IO/M as inputs.
To get some more idea please read this application note
available at,
ftp://download.intel.com/design/intarch/applnots/29219801.PDF
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