Fig 1: Typical microprocessor memory
configuration
SRAM is generally used for high-speed registers, caches
and relatively small memory banks such as a frame buffer
on a display adapter. In contrast, the main memory in a
computer is typically dynamic RAM (DRAM, D-RAM).
An SRAM is designed to fill two needs: to provide a direct
interface with the CPU at speeds not attainable by DRAMs
and to replace DRAMs in systems that require very low power
consumption. In the first role, the SRAM serves as cache
memory, interfacing between DRAMs and the CPU.
The second driving force for SRAM technology is low power
applications. In this case, SRAMs are used in most portable
equipment because the DRAM refresh current is several orders
of magnitude more than the low-power SRAM standby current.
Many categories of industrial and scientific subsystems,
automotive electronics, and similar, contains static RAM.
Several megabytes of SRAM may be used in complex products
such as digital cameras, cell phones, synthesizers, etc.
SRAM is also used in personal computers, workstations,
routers and peripheral equipment: internal CPU caches and
external burst mode SRAM caches, hard disk buffers, router
buffers, etc. LCD screens and printers also normally employ
SRAM to hold the image displayed or to be printed. Small
SRAM buffers are also found in CDROM and CDRW drives to
buffer track data, which is transferred in blocks instead
of as single values. The same applies to cable modems and
similar equipment connected to computers.
SRAM Cell:
The SRAM cell consists of a bi-stable flip-flop connected
to the internal circuitry by two access transistors. When
the cell is not addressed, the two access transistors are
closed and the data is kept to a stable state, latched within
the flip-flop. The flip-flop needs the power supply to keep
the information. The data in an SRAM cell is volatile (i.e.,
the data is lost when the power is removed). However, the
data does not "leak away" like in a DRAM, so the
SRAM does not require a refresh cycle.
Static RAM is fast because the six-transistor configuration
(shown in Fig 2) of its flip-flop circuits keeps current
flowing in one direction or the other (0 or 1). The 0 or
1 state can be written and read instantly without waiting
for a capacitor to fill up or drain (like in DRAM). However,
the six transistors take more space than DRAM cells made
of one transistor and one capacitor.
When opposite voltages are applied to the column wires,
the flip-flop is oriented in one of two directions for a
0 or 1. At that point, the flip-flop becomes a self-perpetuating
storage cell as long as a constant voltage is applied.
Random access means that locations in the memory can be
written to or read from in any order, regardless of the
memory location that was last accessed. Earlier asynchronous
static RAM chips performed read and write operations sequentially.
Newer synchronous static RAM chips overlap reads and writes.
Contrast with dynamic RAM.
Other types of SRAM Cells:
The SRAM cells are categorized based on the type of load
used in the elementary inverter of the flip-flop cell. There
are commonly three types of SRAM memory cells:
1. 4T cell (four NMOS transistors plus two poly load resistors)
2. 6T cell (six transistors-four NMOS transistors plus two
PMOS transistors)
3. TFT cell (four NMOS transistors plus two loads called
TFTs)
4T (Four Transistor) Cell:
This design consists of four NMOS transistors plus two
poly-load resistors. Two NMOS transistors are pass-transistors.
These transistors have their gates tied to the word line
and connect the cell to the columns. The two other NMOS
transistors are the pull-downs of the flip-flop inverters.
The loads of the inverters consist of a very high poly-silicon
resistor. The cell needs room only for the four NMOS transistors.
The poly loads are stacked above these transistors. Although
the 4T SRAM cell may be smaller than the 6T cell, it is
still about four times as large as the cell of a DRAM cell.
Fig 3: 4 Transistor
- SRAM cell
The complexity of the 4T cell is to make a resistor load
high enough (in the range of giga-ohms) to minimize the
current. However, this resistor must not be too high to
guarantee good functionality. Despite its size advantage,
the 4T cells have several limitations
1. Each cell has current flowing in one resistor. (i.e.,
the SRAM has a high standby current)
2. The cell is sensitive to noise and soft error because
the resistance is so high
3. The cell is not as fast as the 6T cell.
6T (Six Transistor) Cell
A different cell design that eliminates the above limitations
is the use of a CMOS flip-flop. In this case, the load is
replaced by a PMOS transistor. This SRAM cell is composed
of six transistors, one NMOS transistor and one PMOS transistor
for each inverter, plus two NMOS transistors connected to
the row line (as shown in fig 2). This configuration is
called a 6T Cell. This cell offers better electrical performances
(speed, noise immunity, standby current) than a 4T structure.
TFT (Thin Film Transistor) Cell
This new structure reduces the current flow through the
resistor load of the old 4T cell. This change in electrical
characteristics of the resistor load is done by controlling
the channel of a transistor. This resistor is configured
as a PMOS transistor and is called a thin film transistor
(TFT). It is formed by depositing several layers of polysilicon
above the silicon surface. The source/channel/ drain is
formed in the polysilicon load. The gate of this TFT is
polysilicon and is tied to the gate of the opposite inverter
as in the 6T cell architecture. The oxide between this control
gate and the TFT polysilicon channel must be thin enough
to ensure the effectiveness of the transistor. The performance
of the TFT PMOS transistor is not as good as a standard
PMOS silicon transistor used in a 6T cell.
Fig 4: Thin Film Transistor (TFT)
SRAM cell
This type of cell posses' complex technology compared to
the 4T cell technology and poor TFT electrical characteristics
compared to a PMOS transistor.
In addition to such SRAM types, other kinds of SRAM chips
use 8T, 10T, or more transistors per bit. This is sometimes
used to implement more than one (read and/or write) port,
which may be useful in certain types of video memory and
register files implemented with multi ported SRAM circuitry.
Memory cells that use fewer than 6 transistors such as 3T
or 1T cells are DRAM, not SRAM.
Classification of SRAM by transistor type:
1. Bipolar junction transistor (used in TTL and ECL): very
fast but consumes a lot of power
2. MOSFET (used in CMOS): low power and very common today
Classification of SRAM by function:
1. Asynchronous: independent of clock frequency; data in
and data out are controlled by address transition.
2. Synchronous: As computer system clocks increased, the
demand for very fast SRAMs necessitated variations on the
standard asynchronous fast SRAM. The result was the Synchronous
SRAM (SSRAM). Synchronous SRAMs have their read or write
cycles synchronized with the microprocessor clock and therefore
can be used in very high-speed applications. An important
application for synchronous SRAMs is cache SRAM used in
PCs. SSRAMs typically have a 32 bit output configuration
while standard ASRAMs have typically a 8 bit output configuration.
All timings are initiated by the clock edge(s). Address,
data in and other control signals are associated with the
clock signals.
Classification of SRAM by feature:
1. ZBT (zero bus turnaround): the turnaround is the number
of clock cycles it takes to change access to the SRAM from
write to read and vice versa. The turnaround for ZBT SRAMs
or the latency between read and writes cycle is zero. In
short the ZBT is designed to eliminate dead cycles when
turning the bus around between read and writes and reads.
2. Sync-Burst (synchronous-burst SRAM): features synchronous
burst write access to the SRAM to increase write operation
to the SRAM.
3. DDR SRAM: Synchronous, single read/write port, double
data rate IO. It increases the performance of the device
by transferring data on both edges of the clock.
4. Quad Data Rate SRAM: Synchronous, separate read &
write ports, double data rate IO
5. Pipelined SRAM: They (also called register to register
mode SRAM) add a register between the memory array and the
output. Pipelined SRAMs are less expensive than standard
ASRAMs for equivalent electrical performance. The pipelined
design does not require the aggressive manufacturing process
of a standard ASRAM.
6. Late-Write SRAM: Late-write SRAM requires the input data
only at the end of the cycle.
SRAM-Cell operation:
Each bit in an SRAM is stored on four transistors that
form two cross-coupled inverters (as shown in Fig 2). This
storage cell has two stable states, which are used to denote
0 and 1. Two additional access transistors serve to control
the access to a storage cell during read and write operations.
A typical SRAM uses six MOSFETs to store each memory bit
and the explanation here is based on the same.
Access to the cell is enabled by the word line which controls
the two access transistors M5 and M6 which, in turn, control
whether the cell should be connected to the bit lines: -BL
and BL. They are used to transfer data for both read and
write operations. Although it is not strictly necessary
to have two bit lines, both the signal and its inverse are
typically provided to improve noise margins.
During read accesses, the bit lines are actively driven
high and low by the inverters in the SRAM cell. This improves
SRAM bandwidth compared to DRAMs. In a DRAM, the bit line
is connected to storage capacitors and charge sharing causes
the bit-line to swing upwards or downwards. The symmetric
structure of SRAMs also allows for differential signaling,
which makes small voltage swings more easily detectable.
Another difference with DRAM that contributes to making
SRAM faster is that commercial chips accept all address
bits at a time. By comparison, commodity DRAMs have the
address multiplexed in two halves, i.e. higher bits followed
by lower bits.
An SRAM cell has three different states it can be in:
1. Standby where the circuit is idle
2. Reading when the data has been requested
3. Writing when updating the contents
Standby: If the word line is not asserted, the access transistors
M5 and M6 disconnect the cell from the bit lines. The two
cross-coupled inverters formed by M1 - M4 will continue
to reinforce each other as long as they are disconnected
from the outside world.
Read operation: Assume that the content of the memory is
a 1, stored at Q. The read cycle is started by pre-charging
both the bit lines to a logical 1, then asserting the word
line WL, enabling both the access transistors. The second
step occurs when the values stored in Q and -Q are transferred
to the bit lines by leaving BL at its pre-charged value
and discharging -BL through M1 and M5 to a logical 0. On
the BL side, the transistors M4 and M6 pull the bit line
toward VDD, a logical 1. If the content of the memory was
a 0, the opposite would happen and -BL would be pulled toward
1 and BL toward 0.
Write operation: The value to be written is applied to
the bit-lines to start the writing operation. To write a
0, we would apply a 0 to the bit lines, i.e. setting -BL
to 1 and BL to 0. This is similar to applying a reset pulse
to a SR-latch, which causes the flip-flop to change state.
A 1 is written by inverting the values of the bit lines.
WL is then asserted and the value that is to be stored is
latched in. Note that the reason this works is that the
bit line input-drivers are designed to be much stronger
than the relatively weak transistors in the cell itself,
so that they can easily override the previous state of the
cross-coupled inverters. Careful sizing of the transistors
in an SRAM cell is needed to ensure proper operation.
To work properly and to ensure that the data in the cell
will not be altered, the SRAM must be supplied by a Vdd
(power supply) that will not fluctuate beyond plus or minus
five or ten percent of the main VCC. If the cell is not
disturbed, a lower voltage level is acceptable to ensure
that the cell will correctly keep the data. In that case,
the SRAM is set to a retention mode where the power supply
is lowered, and the part is no longer accessible.
The power consumption of SRAM varies depending on how frequently
it is accessed; it can be as power-hungry as dynamic RAM,
when used at high frequencies. On the other hand, SRAM used
at a somewhat slower pace, such as in applications with
moderately clocked microprocessors, draw very little power
and can have nearly negligible power consumption when sitting
idle.
SRAM Interface:
Basic Connection:
The pin connections common to all type of memory devices
(including SRAM) are the address inputs, data I/O, some
type of selection input and at least one control input used
to select a read or write operation.
Fig 5: Basic memory
component connections
The address inputs are used to connect or select a memory
location within the memory device. The memory device that
has 10 address lines will be having its address pins labeled
from A0 (Least Significant) to A9. The number of memory
address pins found on a memory device is determined by the
number of memory locations found within it. The data I/O
connections are the points at which the data are entered
for storage or extracted for reading. Today the memory devices
are equipped with bi-directional common data I/O lines.
The SRAM has an input that selects or enables the memory
device, called chip select (CS). If this pin is active (a
logic 0 applied at this pin) the memory device performs
a read or a write operation.
The other two control inputs associated with SRAM are Write
Enable (WE) and Output (also called read enable) Enable
(OE). Sometimes the (WE) is labeled as (W) and the (OE)
is labeled as (G). The write enable pin must be made active
(applying logic 0) to perform a memory write operation and
the (OE) must be active to perform a read operation from
the memory. But they must never both be active at the same
time.
Fig 6 shows a typical functional block diagram and a typical
pin configuration of an asynchronous SRAM (from cypress).
Fig 6: Asynchronous
SRAM- Logical & pin diagrams
Interfacing SRAM with 8051:
Let us now try to understand how to Interface/interconnect
an external static RAM (SRAM) to an 8051 microcontroller.
It shows how to interface a generic SRAM to a C8051 device
using standard GPIO port pins.
Fig7: SRAM interface
to 8051
The interface uses a multiplexed address and data bus to
reduce the number of port pins required. The lower address
bits are held in a latch while data is transferred. Fig
7 shows the block diagram of the hardware connection between
the 8051 microcontroller and the SRAM.
The multiplexed address/data bus 'AD[7..0]' support the
lower 8 bits of the address and the 8 bits of data. This
configuration allows the lower address lines to be held
by the latch while the SRAM and 8051 transfer data, such
that 8 additional ports for data transfer are not necessary.
The 'A[15..8]' supply the upper 8 bits of the address.
'A16' acts as a bank select between the two 64 Kbyte banks.
A '0' is bank one and '1' is bank two.
'RD' is the read strobe (operates active low). 'WR' is the
write strobe (operates active low). 'ALE' is the address
latch signal that holds the lower 8 address bits during
data transfer. 'CS' is the SRAM chip select (operates active
low).
The following figures show the timing diagrams for a typical
read and write operation.
Fig8: Start of Frame
packet format
To read another more detailed article on SRAM interface,
download the application note from Si Labs at,
https://www.silabs.com/Support%20Documents/TechnicalDocs/an106.pdf
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